The present invention relates to a delay circuit and related method thereof, and particularly relates to a delay circuit utilizing a mapping table to select proper number of delay stages, and related method thereof.
FIG. 1 illustrates a circuit diagram of a related art delay circuit 100. The delay circuit 100 includes a plurality of delay stages 101, 103, 105 (only part of the delay stages are illustrated) to 10n, and utilizes a selection signal SS to select a number of the delay stages to delay the input data signal Datain by a desired delay amount in order to generate a desired output data signal Dataout. However, many factors such as temperature, process, the lines between the elements of the delay circuit 100 or the delay amount generated by the elements themselves will affect the delay circuit 100, such that the selected delay stages may provide an undesired delay amount.
One example of the above-mentioned defects is that the delay circuit will be non-monotonic. Such disadvantages are especially apparent for a high resolution delay circuit. In this situation, chose more delay stages but may provide a less delay amounts, therefore a serious mismatching problem will occur.